
Silicon Carbide (SiC) Technology at A*STAR IME
Introduction
At the Institute of Microelectronics (IME), our Silicon Carbide Research Group leads in SiC innovation with a cutting-edge 200mm R&D SiC line. Developed in collaboration with global industry leaders, this facility enables rapid prototyping, precision validation, and seamless scaling of technologies from the lab to pilot production. Our efforts address complex industry challenges, providing the power electronics ecosystem with innovative solutions that drive progress and inspire breakthroughs.
Research Areas
SiC Epitaxy and Defect Characterization
The foundation of high-performing SiC power devices lies in defect-free epitaxial layers. Even minor defects such as basal plane dislocations (BPDs) and micropipes can severely impact device reliability. IME focuses on refining epitaxial growth processes to achieve superior uniformity and reduce defect densities, ensuring high-quality substrates for advanced applications such as power electronics and high-power.
Collaborations:
: Joint development of 200mm SiC substrates using Soitec’s Smart Cut™ technology, integrated with IME’s pilot production expertise, enhances MOSFET processes for these substrates for device yield and performance. By developing advanced epitaxy solutions, the collaboration aims to create a benchmark for SiC MOSFET devices, driving innovation in the SiC ecosystem and supporting high-volume manufacturing in the future.
(An ASM Company): Partnership on the development of high-quality 200mm SiC epitaxy processes and optimizing epitaxial growth rates and material properties using LPE’s cutting-edge CVD (chemical vapor deposition) reactor technology. In this collaboration, the goal is to reduce killer defect densities while optimizing material properties, ultimately contributing to the development of next-generation SiC devices with superior performance and reliability.​
SiC Power MOSFET Design, Fabrication, and Testing
IME addresses the entire SiC MOSFET value chain, from conceptual design to fabrication and rigorous testing.
Design and Simulation: Leveraging TCAD (Technology Computer-Aided Design) simulations to model next-generation MOSFETs that deliver higher switching speeds, better energy efficiency, and superior thermal management. With the industry's transition to higher current ratings and larger chip areas, improving on-state resistance is crucial. We are exploring novel gate dielectric materials and unique processing methods to reduce this resistance, pushing the boundaries of SiC power electronics for applications such as electric vehicles and renewable energy systems.
Fabrication: A dedicated 200mm SiC line supports pilot-scale manufacturing, accelerating the development cycle from prototype to production. We are pioneering approaches to reduce yield-killer defects in SiC epilayers, such as BPDs (basal plane dislocations), during fast growth epitaxy, which are critical as the industry moves towards larger chip areas with lower on-state resistance.
Testing: Automated and semi-automated integrated solutions to rigorously validate static and dynamic performance of SiC devices’ reliability under extreme conditions, ensuring innovation aligns with industry standards. By bridging simulation, fabrication, and testing, we ensure that SiC MOSFETs are not only innovative but also meet the stringent demands of the power electronics industry, driving the development of high-efficiency, next-generation SiC power electronics.
SiC Gate Dielectric and MOS Interface Development
The gate dielectric and MOS interface play pivotal roles in optimizing device performance by minimizing leakage currents, enhancing breakdown strength, and stabilizing threshold voltages for advancing the performance and reliability of SiC-based power devices.
Research Focus:
Refining traditional and novel dielectric materials.
Address defects at the SiC/dielectric interface to boost channel mobility and reduce charge traps, hence reducing leakage currents, improving threshold voltage stability, and boosting overall device efficiency for high-performance applications.
Key Partnerships:
centrotherm: Collaboration on advanced diffusion and annealing tools for optimized trench and gate oxide formation in 200mm SiC devices. This collaboration is enhancing SiC device performance through optimized trench and gate oxide formation. This collaboration explicitly targets applications such as electric vehicles and power grids.
Material characterization tools:
Through these efforts and our state-of-the-art material characterization tools, we are supporting the development of next-generation SiC devices with superior reliability and efficiency. This research is crucial for meeting the increasing demands of industries like electric vehicles and renewable energy systems, pushing the boundaries of SiC device capabilities.
SiC Ohmic and Schottky Contacts
Reliable ohmic and Schottky contacts are essential for high-efficiency SiC devices to reduce power losses and enhance device efficiency.
Focus Areas:
Reducing contact resistance for improved current flow in ohmic contacts. Ohmic contacts are crucial for establishing low-resistance connections between metal and semiconductors, ensuring efficient current flow.
Enhancing rectification performance and reducing leakage currents in Schottky contacts.
Improve the electrical performance and efficiency of SiC devices by addressing critical contact types and innovating new materials and processing techniques to meet demands for high-power and high-frequency applications.
SiC Power Packaging Module Development
Packaging is critical for thermal management, electrical insulation, and mechanical stability in high-power SiC devices.
Key Innovations:
Development of advanced power module designs capable of withstanding junction temperatures up to 200°C.
Proprietary interconnection techniques and cooling systems, such as double-sided liquid cooling, for next-gen applications like 6-in-1 modules.
Collaborations:
Toray Industries, Inc.: Joint efforts to develop next-generation power module packaging materials to improve the efficiency and reliability of SiC power modules that are crucial for high-performance applications like electric vehicles and renewable energy systems.
Shaping the Future of SiC Technology
A*STAR IME is at the forefront of SiC innovation through our comprehensive research and strong industry partnerships. We are driving technological advancements to unlock the full potential of SiC in power electronics, supporting industries in achieving high-performance, energy-efficient solutions for a sustainable future.
Collaborations
IME x STMicroelectronics
Read MoreIME x SOITEC (Epitaxy)
IME x LPE (epitaxy)
IME x Centrotherm (SiC Gate Dielectric and MOS Interface)
Read MoreInfrastructure that we have

LPE (ASM) PE108:
- 150mm/200mm Single wafer SiC Epi-reactor cassette to cassette operation
- High through-put: one standard run in < 75 minutes (10 µm drift layer SiC epi for 1200V devices, high growth rate of 50 µm/h)

Implanter from Nissin
Highlights of papers/publications
No. | Name of paper | Author(s) | Conf | Link |
---|---|---|---|---|
1 | Multi-layer high-K gate stack materials for low Dit 4H-SiC based MOSFETs | L. K. Bera, N. Singh, Z. Chen, C. H. M. Chua, K.J. Chui, R. P. Singh, S. Chung, K. M. Han, K. Chong, and D. L. Kwong | ICSCRM 2021 | |
2 | Improvement of Interface Properties for Thermal Oxidized SiO2/SiC MOS capacitor by Post Oxidation Annealing Treatment | U. Chand, L. K. Bera*, N. Singh, K. M. Han, V.Q.G. Roth, C. H. M. Chua, S. Chung | ICSCRM 2022 | |
3 | Gate Dielectric Current Transport Mechanisms in n-SiC Metal Oxide Semiconductor Capacitor | U. Chand, L. K. Bera*, N. Singh, K. M. Han, V.Q.G. Roth, C. H. M. Chua, S. Chung | ICSCRM 2022 | |
4 | Extraction of SiO2/4H-SiC interface trap charge by TCAD simulation | Surasit Chung Lakshmi Kanta Bera, Sun Tao(SILVACO), Zhao Qingda(SILVACO), Navab Singh, Chand Umesh | ICSCRM 2023 | |
5 | Atom probe tomography characterization of SiO2/4H-SiC interface | Surasit Chung Lashmi Kanta Bera, Shiv Kumar, Navab Singh, Chand Umesh, Abdul Hannan Bin Ibrahim Abdullah Yeo, Voo Qin Gui Roth, Pierre Yves Corre(CAMECA Instruments, USA) | ICSCRM 2023 | |
6 | Demonstration of Low Interface Trap Density (~3×1011eV-1cm-2) SiC/SiO2 MOS Capacitor with Excellent Performance using H2+NO POA Treatment for SiC Power Devices | Umesh Chand1,a*, Lakshmi Kanta Bera1,b*, Navab Singh1,c, Tamara Fidler2,d,Patrick Schmid2,e, Shiv Kumar1,f, Voo Qin Gui Roth1,g,Abdul Hannan Bin Ibrahim Abdullah Yeo1,h, Huseyin. Cakmak1,i,Akhil Ranjan1,j, Pavan Vudumula1,k, Marco Camalleri3,l, Laura Scalia3,m,Mario Saggio3,n, Alfio Guarnera3,o, Mooi Kun Teoh3,p, Maurizio Castorina3,q,Surasit Chung1,r | ICSCRM 2023 | |
7 | High-k Gate Dielectric for High-Performance SiC Power MOSFET Technology with Low Interface Trap Density, Good Reliability (ttddb≥ 104s), and High Thermal Stability (≥ 800C) | Umesh Chand1,a*, Lakshmi Kanta Bera1,b*, Navab Singh1,c, Chen Zhixian1,d,Shiv Kumar1,e, Voo Qin Gui Roth1,f, Abdul Hannan Bin Ibrahim Abdullah Yeo1,g,Binni Varghese1,h, Pavan Vudumula1,i, Huseyin. Cakmak1,j, Akhil Ranjan1,k,Lin Huamao1,l, Surasit Chung1,m | ICSCRM 2023 | |
8 | Temperature-Dependent Evaluation of Commercial 1.2 kV, 40 mΩ 4H-SiC MOSFETs: A Comparative Study between Planar, One-side Shielded Trench, and Double Trench Gate Structures | Pavan Vudumula1,a*, Umesh Chand1,b, Lakshmi Kanta Bera1,c,Calvin Chua Hung Ming1,d, Navab Singh1,e, Surasit Chung1,f | ICSCRM 2023 | |
9 | The Effect of Nitrogen Plasma Treatment Process on Ohmic Contact Formation to n-type 4H-SiC | A.H. Yeo1,2,a*, V.Q.G. Roth1,b, L.K. Bera1,c, N. Singh1,d, U. Chand1,e,S. Chung1,f, A. Ranjan1,g, G. Ho1,h, S.K. Lim1,i, and X. Gong2,3,j | ICSCRM 2023 | |
10 | SmartSiCTM Substrates: A Boon to Drain Metallization Process | H. Cakmak1,a, A. Thomas2,b, S.A.H. Ratnaraj2,c, A.H. Yeo1,d*, S. Kumar1,e,H. Xie1,f, U. Chand1,g, P. Vudumula1,h, V.Q.G. Roth1,i, L.K. Bera1,j, N. Singh1,k,S. Chung1,l, L. Kabelaan2,m, I. Radu2,n, W. Schwarzenbach2,o | ICSCRM 2023 | |
11 | Development and Demonstration of a High Temperature and High-Performance Dual Side Cooling SiC Power Module for Automotive Application | Gongyue Tang, Leong Ching Wai, Yong Han | ICSCRM 2024 | |
12 | Indium-Tin-Oxide (ITO) Interlayer-assisted Ohmic Contacts on N-type 4H-SiC with Low Specific Contact Resistance | A.Y. Hannan1,2*, V.Q.G. Roth1, L.K. Bera1, U. Chand1, N. Singh1, N.X. Sang1,S. Kumar1, S. Chung1, J. Xie2, Y.C. Yeo1, and X. Gong2,1 | ICSCRM 2024 | |
13 | BCl3 Plasma Treatment for Enhanced Ohmic Contact Performance to P-type 4H-SiC | A.Y. Hannan1,2*, V.Q.G. Roth1, L.K. Bera1, U. Chand1, N. Singh1, S. Chung1,X. Sang1, Z.J. Quek1,2, A. Ranjan1, V.R. Pavan1, G. Ho1, S.K. Lim1,M. Ozalis1, J. Xie2, Y.C. Yeo1and X. Gong2,1 | ICSCRM 2024 | |
14 | C-Face Epitaxy for Enhanced SiC Device Performance: Insights from Schottky Barrier Diodes | V.Q.G. Roth1, A.Y. Hannan1, L.K. Bera1*, U. Chand1, Y.-C. Chien1,N.X. Sang1, W.D. Song1, S. Kumar1, H.M. Chua1, N. Singh1, S. Chung1,Y. Kam2, M. Zielinski2, L. Kabelaan2, W. Schwarzenbach2, I. Radu2,L. Boudin2 | ICSCRM 2024 | |
15 | Study of SiC trench etching characteristics for different crystal planes | A. Ranjan1, L. K. Bera1, S. Kumar1, H. Lin1, U. Chand1, N. Singh1, S. Chung1,A.Y. Hannan1, V.Q.G. Roth1, A. Sundaram1, L. Liyuan1, and J.W.Y.Kam1 | ICSCRM 2024 | |
16 | Nearly Defect-Free Epitaxy on 150 mm C-Face SiC Substrates | Xuan Sang Nguyen*, Wen Dong Song, Shiv Kumar, Lakshmi Kanta Bera, Navab Singh, Surasit Chung, Eng Soon Tok, Shian Yeu Kam, Marcin Zielinski, Loic Kabelaan, Walter Schwarzenbach, Ionut Radu, Loann Boudin, Yee Chia Yeo | ICSCRM 2024 | |
17 | Inline Methodology for Rapid Characterization of Carrier Mobility in SiC Drift Layer and Wafer Mapping of 200 mm 4H-SiC Wafers | Wen Dong Song*, Shiv Kumar, Xuan Sang Nguyen, Umesh Chand, Lakshmi Kanta Bera, Eng Soon Tok, Surasit Chung, Navab Singh, Yee Chia Yeo | ICSCRM 2024 | |
18 | Achieving Low Dit (~5×1010eV-1.cm-2), Competitive JG (~ 5×10-10 A.cm-2) Performance and Enhanced Post-Stress Flatband Voltage Stability Using Deposited Oxide | Umesh Chand, Yu Chieh Chien, Abdul Hannan Yeo, Qin Gui Roth Voo, Shiv Kumar, Akhil Ranjan, Binni Varghese, Weijie Wang, Pavan Vudumula, Tamara Fidler, Patrick Schmid, Mario Saggio, Maurizio Castorina, Marco Camalleri, Jia Wei Xie, Xiao Gong, Surasit Chung, Lakshmi Kanta Bera, Navab Singh, Yee Chia Yeo | ICSCRM 2024 | |
19 | Defect density reduction in 4H-SiC (0001) epilayer via growth-interruption during buffer layer growth | Shiv Kumar*, Lakshmi Kanta Bera, Xuan Sang Nguyen, Wen Dong Song, An Min Amanda Lee, Xin Yi Li, Eng Soon Tok, Madurai Srinivasan Bharathi, Chilla Damodara Reddy, Umesh Chand, Surasit Chung, Navab Singh, Yee Chia Yeo | ICSCRM 2024 | |
20 | Impact of Single-Step Deep P-Body Implant on 1.2KV 4H-SiC MOSFET | Pavan Vudumula*, Lakshmi Kanta Bera, Umesh Chand, Abdul Hannan Yeo, Surasit Chung, Navab Singh, Yee Chia Yeo | ICSCRM 2024 | |
21 | Study of In-Grown Micropipes in 200 mm 4H-SiC (0001) Epitaxial Substrate | An Min Amanda Lee, Xin Yi Li, Abdul Hannan Yeo, Qin Gui Roth Voo, Shiv Kumar*, Eng Soon Tok, Umesh Chand, Lakshmi Kanta Bera, Hema Lata Rao Maddi, Surasit Chung, Francois Hébert, Navab Singh, Yee Chia Yeo | ICSCRM 2024 |
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