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Over the years our team has developed in-depth understanding of spin-transfer torque (STT) switching and proposed novel solutions to improve memory devices performance in particular from the materials and stack design perspectives. STT writing involves applying currents through an oxide barrier of a magnetic tunnel junction (MTJ). The MTJ resistance is determined by the relative magnetisation directions of FL (free layer) and RL (reference layer). The distinct resistance of the two existing states (AP/ P) correspond to storing a binary ‘1’ or ‘0', respectively. The switching process is affected by various factors, such as the current density, the temperature, and the MTJ size, material selections, and process damages etc.^1-5 Interestingly, the switching speed is less temperature-dependent in the precessional regime and become highly temperature-dependent in the thermal activation regime¹.

One of our recent experimental studies showed non-collinear structure can deliver ∼53% reduction in critical current density in STT switching without compromising on the thermal stability of the devices. This advantage in switching current performance using the non-collinear stack was found to sustain down to ∼20 nm MTJs¹. 

Spin-orbit torque (SOT) is promising for GHz low-power switching of MTJs with high endurance towards integrated low-power computing because of its attractive non-volatile solutions to currently existing power-hungry volatile cache memory technology (static RAM). Realisation of field-free SOT is the most important challenge towards its practical application. Our works towards various schemes for field-free SOT switching, which have scalability and higher performance promise, involve materials studies, device design and characterisation, materials device simulations and CMOS integration.

We are also exploring the fundamental physics of SOT phenomena and optimisation studies. For example, it is important to study and enhance the charge-to-spin conversion efficiency. We use spin-torque ferromagnetic resonance (ST-FMR) to quantify the spin Hall angle and the damping parameters. In particular, enhanced SOT efficiency may be achieved by engineering FM-based heterostructures and interfaces. We recently demonstrated that substantially large effective spin Hall angle can be achieved with proper stack materials selection, one such example is the Ta/ CoFeB/ Pt stack¹. In another study, we investigate the spin-orbit interaction in HM/ CoFe bilayers using first-principles calculations². Charge transfer at the HM/ CoFe interface results in an interfacial electric field, as well as spin and orbit moments at the interfacial heavy atom. Spin-orbit coupling (SOC) with various materials was studied by comparing the SOC strength at the interfacial heavy atom (IHA) with its bulk value at corresponding transition metal. Our work suggests that interfacial electric field plays an essential role in tuning the SOC effect at HM/ CoFe bilayers, which might be exploited for magnetic switching of SOT-based spin-orbitronic devices.

(a) Film Deposition

• Custom-designed Chiron™ PVD system consisting of 8 DC and 2 RF targets, with built-in in-situ atomic layer deposition system, for film deposition on 100 mm wafers and coupons with sub-angstrom precision.

(b) Film Characterisation

• Magnetic analysis using vibrating sample magnetometer (VSM Model EZ11), alternating gradient magnetometer (MicroMag Model 2900) and superconducting quantum interference device (SQUID MPMS). 
• Structural/electronic/chemical analysis using x-ray diffraction (Bruker™ 2D Micro, PANalytical X’Pert™), x-ray reflectivity, x-ray photoelectron spectrometry (Theta Probe XPS) and ellipsometry.
• Electrical analysis using Capres current-in-plane tunneling tool to determine film level tunnelling magnetoresistance and resistance-area with magnetic fields up to 0.6 T.
• Imaging analysis using atomic force and magnetic force microscopy, transmission electron microscopy, scanning electron microscopy elaborated in the following section.

(c) Device Fabrication

• Lithography tools such as EVG™ mask aligner and Elionix™ electron beam lithography (EBL) system with ~1.5 μm and ~10 nm resolution, respectively.
• Reactive ion etch (IntlVac™) for milling. 
• Thermal/electron beam evaporators (EvoVac™) for metallisation.
  

• Atomic force and magnetic force microscopy (DI 3100 SPM & Bruker ICON™) capable of producing non-perturbative, high contrast and spatial resolution images.
• Transmission electron microscopy (JEOL 2100 TEM/Philips CM300 FEGTEM) giving high resolution cross-sectional images for determining spacer roughness, stack thickness, cell profile, as well as elemental mapping of individual layers using energy dispersive x-ray analysis and electron energy loss spectroscopy. The FEI Titan™ is also equipped with Lorentz and holography capabilities for analysing magnetic textures at variable fields and temperatures.
• Magnetic transmission x-ray microscopy at the XM1 beamline in Lawrence Berkeley National Laboratory, USA, with full field transmission x-ray magnetic circular dichroism contrast, for imaging magnetic textures with ~30 nm resolution deposited on thin membranes.
• Device and circuit design modelling (e.g. MuMaX3, OOMMF, VASO, SPICE) leveraging on Petascale supercomputing facilities at the National Supercomputing Centre (NSCC).
  

• Custom-made electrical device testing platforms and probe stations with pulsing capabilities <1 ns and noise levels down to ~1nV.
• Cryostats and physical property measurement system for low temperature magneto-transport measurements (2 K, 9 T).
• ISI Wafer auto-prober capable of conducting device testing modules including TMR, switching voltage, endurance, write error rate, read error rate, breakdown voltage.
• Custom-made high-resolution broadband and spin-torque ferromagnetic resonance systems with frequency range of 67 GHz in magnetic fields up to 1 T and variable temperature operation. 

(a) Device Stack Deposition Tool 

• Singulus Timaris cluster sputtering system with pre-cleaning, annealing, wedge deposition and multi-target (over 20) process modules at 2 Å thickness uniformity.

(b) Copper Protocol Fabrication Line

• Spin coating & developing using Silicon Valley Group SVG 90S
• Lithography using Canon EX5 248 nm DUV Stepper
• Hard mask etch using advanced dielectric etcher (SPTS Etch system) or induced coupled plasma (ICP)-fluorine based chemistry etching (Oxford PlasmaPro System 100 cobra ICP)
• Cell etch using Oxford Ionfab 300Plus (Ion milling)
• Cell passivation and insulation using OIPT Plasmalab System 380
• Descum using Axcelis Ashing System
• Chemical mechanical polishing using Okamoto SPP600S
• Electrode deposition using Singulus Rotaris Cluster System or AMAT Endura System
• Annealing using horizontal annealing furnace

(c) Prototyping

• Simulation packages including industry standard Verilog-A, electronic design automation (EDA) and computer aided drafting (CAD) for the design of a viable integrated circuit consisting of a microscopic electronic circuit array of SOT-based devices.
• Simulated IC designs implemented on testing platform such as field programmable gate arrays (FPGA) and printed circuit boards (PCB) and tested on high speed and precision analogue/digital characterisation circuits and device specific read/write circuits.